Verilog - A Practice Approach 发表于 2024-04-07 分类于 笔记 本文字数: 135 阅读时长 ≈ 1 分钟 Backup of talk on 3/22/2024 from https://ccsgeeks.github.io/ There is a typo in the code block above. It should be: 1234mem = 1 // 1mem += 1 // 3mem = 0 // 0mem -= 1 // 2