Verilog - A Practice Approach

发表于 分类于 本文字数： 135 阅读时长 ≈ 1 分钟

Backup of talk on 3/22/2024 from https://ccsgeeks.github.io/

There is a typo in the code block above. It should be:

1
2
3
4
mem = 1    // 1
mem += 1   // 3
mem = 0    // 0
mem -= 1   // 2